The present invention is related to a linearization technique for analog to digital converters (ADC).
The limited ability to implement an amplifier with gain exactly equal to 2.sup.M, where M is an integer number, limits the achievable linearity of algorithmic and pipelined analog-to-digital converters. Such amplifiers with accurate gain are typically implemented as switched capacitor amplifiers. A switched capacitor amplifier with gain equal to two (X2 amplifier) is shown in FIG. 5. The circuit operates in two phases (FIGS. 1 and 2). In the first phase (sampling phase) the switches labelled .phi..sub.1 are closed connecting the input signal to C.sub.F (feedback capacitor) and C.sub.S (sampling capacitor) as shown schematically in FIG. 1. At the end of the phase the capacitors are disconnected leaving the input voltage stored on each capacitor. In the second phase (amplification phase) the switches labelled .phi..sub.2 are closed as shown schematically in FIG. 2. All charge stored on C.sub.S will be transferred to C.sub.F resulting in the transfer function shown in equation (1) if an infinite operational amplifier open-loop gain is assumed. EQU gain=(C.sub.S +C.sub.F)/C.sub.F (1)
The gain becomes exactly equal to 2 if C.sub.S and C.sub.F are exactly equal. The accuracy of the gain is limited by the capacitor matching that can be obtained with current technology. During one clock cycle, the sampling phase is performed before an amplification phase. For normal operation in a high-speed ADC, the X2 amplifier therefor will alternate between the sampling phase and the hold phase.
Several principles have been proposed to enhance the performance of the X2 amplifier. The mismatch problem is known to be solved by using the same capacitor both for sampling and feedback. This is accomplished by sampling the input twice and transferring the charge back and forth from an extra capacitor. Four operational amplifier (op amp) settling-time periods are required in this solution, and the obtainable conversion rate would therefore be reduced by at least a factor of two.
In FIG. 6 the same configuration as in FIG. 5 is used, except that the circuit is connected so that both C.sub.S and C.sub.F can be used as feedback capacitor. If the capacitances of C.sub.S and C.sub.F are different by a certain percentage, the gain will become higher than two or lower than 2 depending on which of the capacitors is selected as feedback capacitor, cf. equation 1. It is known from prior art to use the value of the input signal V.sub.in, to determine if C.sub.S or C.sub.F should be used as feedback capacitor. When this configuration is used in a so-called pipeline ADC, having several amplifiers, their gain is dependent on the input voltage, hence harmonic distortion in the system results. Therefore this approach cannot improve the distortion of the ADC, measured by the parameters SFDR (spurious free dynamic range), THD (total harmonic distortion) for full scale input signals. The DNL (differential nonlinearity) of the converter is improved.